(a) Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of forming metal lines in a semiconductor device that can prevent or reduce the likelihood of corrosion of the metal during a cleaning process.
(b) Description of the Related Art
Generally, the metal materials that are most frequently used in semiconductor manufacturing processes are aluminum and aluminum alloys. This is because aluminum and aluminum alloys have high electric conductivity and good adherence to an oxide layer, and they are easily formed.
However, aluminum and aluminum alloys have some drawbacks such as electro-migration, hillocks, and spiking.
When an electric current is flowed in an aluminum line used for metal wiring, aluminum atoms in a current concentrating region, such as a contacting area with a silicon layer, or a step-shaped region are easily diffused into other regions. Consequently, the aluminum line may become narrower and broken, and this phenomenon is called electro-migration. Electro-migration occurs by electrons diffusing little by little, and so it occurs after considerable operating time.
In order to overcome such drawbacks, an aluminum-copper alloy where a small quantity of copper (e.g., 0.5-2.0 wt. %) is added to aluminum can be used, and the resulting aluminum line may have improved step coverage and an enlarged contact area.
Another problem may happen in an alloying process. That is, a junction spike phenomenon may occur where silicon atoms in the substrate diffuse into an overlying aluminum layer during heat treatment.
The junction spike phenomenon can be suppressed by using an aluminum-silicon alloy that is formed by adding excess silicon or by forming a diffusion barrier including a thin metal (e.g., TiW or PtSi) layer between an aluminum layer and a silicon substrate.
Accordingly, an alternative material for the metal lines has been demanded. A high conductive metal, such as copper (Cu), gold (Au), silver (Ag), cobalt (Co), chrome (Cr), and nickel (Ni), can be a candidate for the alternative material. Among these metals, copper and copper alloys are widely adopted owing to low resistivity, high reliability against electro-migration and stress-migration, and low manufacturing cost.
The copper and copper alloys are deposited into a via hole (or a contact hole) and a trench in a dual damascene structure and polished by chemical mechanical polishing so as to form a copper line. However, the copper line is easily oxidized and dissolved by a slurry used in a chemical mechanical polishing process, so it is difficult to be planarized.
A conventional method of forming a metal line in a semiconductor device will hereinafter be described in detail with reference to the accompanying drawings.
FIG. 1A to FIG. 1D are cross-sectional views showing principal stages of forming a conventional metal line in a semiconductor device.
As shown in FIG. 1A, a first insulation layer 12 is formed on a semiconductor substrate 11, and a first conductive layer (e.g., a copper layer) is formed thereon. Subsequently, the first conductive layer is selectively etched by a photo and etching process so as to form a first metal line 13.
A second insulation layer 14 is formed on the entire surface of the semiconductor substrate 11 including the first metal line 13, and a first photosensitive layer 15 is coated on the second insulation layer 14. Subsequently, the first photosensitive layer 15 is selectively patterned by an exposure and development process so as to define a contact region. The patterned first photosensitive layer 15 is used as an etching mask in selectively etching the second insulation layer 14 to expose a part of the surface of the first metal line 13, thereby forming a via hole 16.
As shown in FIG. 1B, after the first photosensitive layer 15 is removed, a second photosensitive layer 17 is coated on the semiconductor substrate 11 and patterned by an exposing and developing process so as to define a wiring region. Subsequently, the exposed second insulation layer 14 is selectively etched by using the patterned second photosensitive layer 17 as an etching mask so as to form a trench 18 having a predetermined depth. The trench 18 is located on the via hole 16 and has a greater width than the via hole 16 so as to form a dual damascene structure.
In forming the trench 18 and the via hole 16, etching residues 19 are unavoidably generated.
As shown in FIG. 1C, after removing the second photosensitive layer 17, a dry cleaning process is performed over the semiconductor substrate 11 provided with the trench 18 and the via hole 16 so as to remove the etching residues 19.
A single wafer type cleaning apparatus is generally used for the cleaning process. The cleaning process using the single wafer cleaning apparatus generally has a better cleaning ability than another cleaning process (e.g., a batch wafer cleaning apparatus and/or a wet cleaning process) using deionized (DI) water.
In using the single wafer type cleaning apparatus, a wafer is rotated at a high RPM (e.g., 100-2000RPM) and accelerated. In addition, a chemical, such as a nitrogen (N2) gas, is sprayed onto the wafer so as to remove the etching residues 19 in the trench 18 and the via hole 16.
As shown in FIG. 1D, after the cleaning process, a conductive barrier layer 20 and a second conductive layer 21 (e.g., a copper layer) are sequentially formed over the entire surface of the semiconductor substrate 11 including in the trench 18 and the via hole 16. Subsequently, a chemical mechanical polishing (CMP) process is performed over the semiconductor substrate 11 in order to remove the second conductive layer 21 and the barrier layer 20 from areas outside the via hole 16 and the trench 18, and leave the second conductive layer 21 and the barrier layer 20 in the via hole 16 and the trench 18.
According to the conventional method, during the process of spraying a chemical at high RPM in the single wafer type cleaning apparatus, a high level of static electricity may be generated in a region of the apparatus and/or wafer, wherein charges are locally increased, and the first metal line 13 may “explode” (or otherwise become catastrophically damaged).
The explosion phenomenon cannot be found by a general in-line inspection tool, and so it can only be found after completing the process of forming the device. This can be a serious factor in deteriorating the yield of the device.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore, it may contain information that does not form knowledge or other form of prior art that may be already known in this or another country to a person of ordinary skill in the art.